# SPDX-License-Identifier: GPL-2.0-or-later


# Choose debugger
source [find interface/stlink.cfg]

# Choose transport interfance 
transport select hla_swd

# Set chip name
set CHIPNAME STM32H7B0VBT6

# Enable stmqspi
if {![info exists OCTOSPI1]} {
	set OCTOSPI1 1
	set OCTOSPI2 0
}

# Use built-in stm32h7 openocd configs
source [find target/stm32h7x.cfg]

reset_config none separate

# OCTOSPI initialization
proc octospi_init { octo } {
	global a b
	mmw 0x58024540 0x000006FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
	mmw 0x58024534 0x00284000 0				;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
	sleep 1									;# Wait for clock startup

	mww 0x5200B400 0x00ff0000				;# 
	mww 0x5200B404 0x03010101				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
	mww 0x5200B408 0x07050333				;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1

	# mmw command: "memory modify word, modify only given bits"
	# usage: mmw "address setbits clearbits"

	# PA07:AF10:V, PA06:AF06:V, PB06:AF10:V, PB02:AF09:V, PB01:AF11:V, PD12:AF09:V
	# PE10:AF10:V, PE09:AF10:V, PE08:AF10:V, PE07:AF10:V
	# Port A: PA07:AF10:V, PA06:AF06:V
	mmw 0x58020000 0x0000A000 0x00005000	;# MODER
	mmw 0x58020008 0x0000F000 0x00000000	;# OSPEEDR
	mmw 0x5802000C 0x00000000 0x0000F000	;# PUPDR
	mmw 0x58020020 0xA6000000 0x59000000	;# AFRL
	# Port B: PB06:AF10:V, PB02:AF09:V, PB01:AF11:V
	mmw 0x58020400 0x00002028 0x00001014	;# MODER
	mmw 0x58020408 0x0000303C 0x00000000	;# OSPEEDR
	mmw 0x5802040C 0x00000000 0x0000303C	;# PUPDR
	mmw 0x58020420 0x0A0009B0 0x05000640	;# AFRL
	# Port D: PD12:AF09:V
	mmw 0x58020C00 0x02000000 0x01000000	;# MODER
	mmw 0x58020C08 0x03000000 0x00000000	;# OSPEEDR
	mmw 0x58020C0C 0x00000000 0x03000000	;# PUPDR
	mmw 0x58020C24 0x00090000 0x00060000	;# AFRH
	# Port E: PE10:AF10:V, PE09:AF10:V, PE08:AF10:V, PE07:AF10:V
	mmw 0x58021000 0x002A8000 0x00154000	;# MODER
	mmw 0x58021008 0x003FC000 0x00000000	;# OSPEEDR
	mmw 0x5802100C 0x00000000 0x003FC000	;# PUPDR
	mmw 0x58021020 0xA0000000 0x50000000	;# AFRL
	mmw 0x58021024 0x00000AAA 0x00000555	;# AFRH

	# OCTOSPI1: Use 1-1-1 read and 0x03 read data command
	mww 0x52005000 0x30400f4B				;# OCTOSPI_CR: FMODE=11, APMS=1, FTHRES=16, FSEL=0, DQM=0, TCEN=1
	mww 0x52005008 0x00170108				;# OCTOSPI_DCR1: MTYP=0x0, FSIZE=0x17=23=2^(23+1), CSHT=01, CKMODE=0, DLYBYP=1
	mww 0x5200500C 0x00000001				;# OCTOSPI_DCR2: WRAPSIZE=0, PRESCALER=0+1

	mww 0x52005100 0x01002101				;# OCTOSPI_CCR: SIOO=0, DMODE=001, ABSIZE=00, ABMODE=000, ADSIZE=10, ADMODE=001, ISIZE=0x0, IMODE=001
	mww 0x52005108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
	mww 0x52005110 0x00000003				;# OCTOSPI_IR: INSTR=ReadData, 0x03

	sleep 1

	flash probe $a							;# load configuration from CR, TCR, CCR, IR register values
}

$_CHIPNAME.cpu0 configure -event reset-init {
	global OCTOSPI1
	global OCTOSPI2

	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for  64MHZ HCLK

	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
	mww 0x58024418 0x00000040				;# RCC_CDCFGR1: CDCPRE=1, CDPPRE=2, HPRE=1
	mww 0x5802441C 0x00000440				;# RCC_CDCFGR2: CDPPRE2=2, CDPPRE1=2
	mww 0x58024420 0x00000040				;# RCC_SRDCFGR: SRDPPRE=2
	mww 0x58024428 0x00404040				;# RCC_PLLCKSELR: DIVM3=4, DIVM2=4, DIVM1=4, PLLSRC=HSI
	mww 0x5802442C 0x01ff0ccc				;# RCC_PLLCFGR: PLLxRGE=8MHz to 16MHz, PLLxVCOSEL=wide
	mww 0x58024430 0x01010207				;# RCC_PLL1DIVR: 64MHz: DIVR1=2, DIVQ1=2, DIVP1=2, DIVN1=8
	mww 0x58024438 0x01010207				;# RCC_PLL2DIVR: 64MHz: DIVR2=2, DIVQ2=2, DIVP2=2, DIVN2=8
	mww 0x58024440 0x01010207				;# RCC_PLL3DIVR: 64MHz: DIVR3=2, DIVQ3=2, DIVP3=2, DIVN3=8
	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
	sleep 1
	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
	sleep 1

	adapter speed 4000

	if { $OCTOSPI1 } {
		octospi_init 0
	}
}